Evaluation of the OneChip Reconfigurable Processor

The concept of a reconfigurable processor comes from the idea of having a general-purpose processor coupled with some reconfigurable resources that allow implementation of custom application-specific instructions. This thesis describes OneChip, a third generation reconfigurable processor architecture that integrates a Reconfigurable Functional Unit (RFU) into a superscalar Reduced Instruction Set Computer (RISC) processor’s pipeline. The architecture allows dynamic scheduling and dynamic reconfiguration. To evaluate the performance of the OneChip architecture, several off-the-shelf software applications were compiled and executed on Sim-OneChip, an architecture simulator for OneChip which includes a software environment for programming the system. The architecture is compared to a similar one but without dynamic scheduling and without an RFU. OneChip achieves a performance improvement and shows a speedup range from 2.16 up to 32.02 for the different applications and data sizes used.